1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of testing integrated circuits to determine the effects of various processes upon the reliability of the circuits.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS and as well as metal insulator semiconductor (MIS) technologies are currently among the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. Generally, MOS technology involves forming a poly/metal gate, as well as dielectric and semiconductor substrates.
Various processes are performed on semiconductor substrates in manufacturing integrated circuit products. When integrated circuits are formed, tests are performed to determine the correctness in the operation of the circuits. Manufacturers generally perform various tests to determine the effects of the various processes on the performance and reliability of the circuits. Various quality or performance criterions may be used in determining whether the integrated circuits meet quality standards.
Dielectric weakening and/or failure with respect to time, temperature, and/or voltage are major concerns with regard to reliability failure of circuits manufactured using current semiconductor technology. In some instances, defects during processing can lead to dielectric failure (e.g., time dependent dielectric breakdown (TDDB) failure mechanism), or a parametric shift known as bias temperature instability (BTI) failure mechanism, either of which may result in a decrease in the overall reliability of the semiconductor devices. Process problems may affect the characteristics of the transistors and/or may cause weakening or failure of dielectric, which may lead to problems such as loss of integrity of the gate of a transistor. Therefore, tests to check various failure mechanisms (TDDB/BTI) are performed for testing the reliability of the integrated circuits.
Manufacturers generally perform tests that help determine the dielectric failure prospects in order to determine the reliability of the circuits. Generally, two primary tests are performed in order to determine the dielectric failure prospects: a TBBD test and a BTI test. Generally, these tests are performed individually on different devices.
The TDDB test relates to determining when a circuit portion, such as the gate of a MOSFET device, breaks down. This may be caused by weakness in portions of the dielectric. A determination may be made as to when the dielectric part of the circuit portion breaks down at certain particular current-levels, voltage levels, and/or temperature levels. In the example of a MOSFET, the breakdown would keep the gate of the MOSFET from operating properly as a switch that could control the current flow through the source and the drain of the MOSFET.
The BTI test relates to determining a shift in linear and saturation threshold voltages and/or linear and saturation currents, for example, of a transistor. In some cases, due to contamination during process, or due to other process problems, the threshold voltage may shift to a higher voltage. In this case, a higher voltage would be required to turn on, for example, a gate of a transistor. In addition, with continuous usage of a product (i.e., integrated chip), the MOSFET device may suffer degradation of its characteristics (e.g., threshold voltage, linear current, saturation current, etc.) due to time, temperature and/or voltages, etc. The BTI test may reveal whether the amount of shift (at time zero or within the lifetime of the product) in the linear and saturation threshold voltages, linear current, and/or saturation current would cause operational problems in a component, such as a transistor.
A voltage ramp Stress (VRS) test may be used to perform the TDDB and BTI tests. FIG. 1 illustrates a prior art VRS test signal used for a TDDB test and/or a BIT test. As indicated in FIG. 1, the stress voltage is supplied to the gate and/or substrate while other terminals are grounded, wherein the stress voltage is ramped up in steps. The steps are characterized by a change in voltage of ΔV during a time period of ΔT. The signal in FIG. 1 contains intermediate monitoring steps for verification of dielectric breakdown. The dielectric breakdown may be determined from monitoring current and/or stress current.
As an example, in processes involving metal-gate/High-k stack (MG/HK), fast process screening is important due to the introduction of new materials, resulting in enhanced process complexity and generating new instability such as the positive-bias temperature instabilities. Tests using VRS signals may also be used to assess dielectric breakdown for conventional ultrathin SiON gate dielectrics with poly-Si electrodes.
FIG. 2 illustrates a prior art VRS test signal used for a BTI test. FIG. 2 illustrates two graphs (202 and 204). Graph 202 plots a stress voltage signal 230 applied to the gate of a transistor, with respect to time. Graph 204 illustrates the corresponding drain voltage (VD) or source voltage (VS) during that time. Graph 202 shows a voltage applied to the gate in a step-wise manner, increasing up to the pre-step 210 level. Prior to starting the stress voltage, a reference drain current (IId) and a reference gate current (IIg) are measured. These reference currents (before and after the stress cycles) may be compared to actual sensed currents in order to check the threshold and/or saturation current integrity.
At the start time tstart, a stress voltage is provided to the gate, wherein the value of the stress voltage is above the gate sense voltage (VG_sense). The application of the stress voltage is brought back to the VG_sense level for performing the sensing function. Subsequently, a stepped-up stress voltage is applied, followed by bringing the stress voltage back to the VG_sense level. This stepwise increase is repeated until a pre-defined voltage, Vstop, a predetermined amount of parametric shift, or stop time, tstop. The stress voltage signal 230 rises in steps 220. The time period of the stress voltage applied at each step is stress time (tstress) 240. The time period of the sensing function, wherein the stress voltage is brought down to the VG_sense is the sense time (tsense) 250. Based upon performing the stress and sense function, the shift in the threshold voltage, linear current, and/or saturation current of a transistor may be determined. Moreover, there may be variants for the drain voltage, i.e., various levels of the drain voltage, wherein the drain voltage may be in provided in steps or in a continuous mode.
FIG. 3 illustrates a flowchart depiction of a prior art process flow for manufacturing and testing semiconductor devices. Integrated circuits are formed on a substrate using a semiconductor manufacturing process (block 110). Various processes are performed on semiconductor substrates in manufacturing integrated circuit products. For example, photolithography, etching, chemical-mechanical polishing (CMP), etc., are some of the processes performed in manufacturing integrated circuit products.
At least a portion of the integrated circuits may be tested in order to determine the effects of processes upon reliability of circuits and/or test structure (block 120). Generally, in state-of-the-art manufacturing of integrated circuits, the tests may include performing a TDDB test on a device (block 122). Upon performing the TDDB test, data relating to the TDDB test is sensed. Moreover, a BTI test may be performed on another device (block 126). Upon performing the BTI test, data relating to the BTI test is sensed (block 128). In this manner, the state-of-the-art manufacturing processes call for performing the TDDB test and the BTI test in a sequential/individual manner on separate devices.
A determination may then be made as to whether the effects of the processes had on the reliability of the integrated circuits are acceptable, based upon the TDDB and the BTI tests (block 130). Upon a determination that the effects that the processes had upon the reliability of the integrated circuits are not acceptable based upon the tests, various modifications to process parameters may be made in order to adjust process steps performed when manufacturing the integrated circuits (block 140). Upon modifying process parameters, additional integrated circuits are formed on substrates and subsequent tests may be performed, as indicated in FIG. 1.
Upon a determination that the process effects upon the reliability of the integrated circuits are acceptable based upon the tests, a certification may be made that the test results are acceptable (block 150). Based upon this certification, manufacturing of the integrated circuits of the existing process parameters may be continued (block 160).
Among the disadvantages of state-of-the-art techniques, which call for performing the tests separately, and on different devices, includes the fact that performing these tests sequentially means that test information from the same device is not received. Other disadvantages include the fact that more time is required when the tests are performed due to the sequential nature of applying the TDDB and BTI tests. This causes a lack of cross-referencing of the test data from both the TDDB and the BTI tests for more efficient cycle. Further, the learning cycle of forming circuits, testing the circuits, providing feedback adjustments, and/or addressing process splits relating different process sets may be made more inefficient using state-of-the-art methodologies.
The present disclosure may address and/or at least reduce one or more of the problems identified above.